ASIC & Firmware Digital Verification Engineer Intern

at  Synopsys

YOU ARE:

A highly motivated, innovative, and independent ASIC/firmware digital verification engineer intern. You thrive in a collaborative environment, working as part of a highly experienced mixed-signal design team. You are passionate about technology and eager to contribute to the verification of current and next-generation Backplane Ethernet, PCIe, SATA, and USB SERDES products. You possess a solid understanding of digital circuit design and a basic understanding of C/C++ and RISC processors. You have hands-on experience in writing test cases in Verilog and SystemVerilog, and you are familiar with scripting languages like Python or Perl and working in a Linux environment. You have knowledge of high-speed digital and mixed-signal design, and you are familiar with industry digital verification methodologies such as VMM/UVM and version control systems like GIT/SVN/Perforce. Your organization and communication skills are exceptional, allowing you to interact effectively with teammates.

• Creating and updating test plans and test cases
• Writing modular constrained-random/coverage-driven Verilog, SystemVerilog, and UVM/VMM testbenches
• Writing SystemVerilog assertions
• Maintaining simulation regressions and debugging RTL and gate-level simulation failures
• Writing functional coverage and performing functional/code/assertion coverage analysis
• Tracking issues in Jira and documenting in Confluence