ASIC Verification Engineer 3

at  Ciena

HOW YOU WILL CONTRIBUTE:

The Wavelogic family of products is widely used in Ciena’s optical fiber transmission solutions and is one of the main contributors to Ciena’s success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital verification engineer will be required to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.

• The digital verification engineer is encouraged to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
• You are held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods.
• You are encouraged to build the verification, functional coverage and formal verification test plans.
• You are accountable for the creation of the test bench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.
• You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function’s designer.
• Reporting on status updates on a regular basis

• The digital verification engineer is encouraged to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
• You are held responsible for the complete and detailed validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods.
• You are encouraged to build the verification, functional coverage and formal verification test plans.
• You are accountable for the creation of the test bench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable.
• You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function’s designer.
• Reporting on status updates on a regular basi