Automotive Digital Design Engineer
at Synopsys
München, Bayern, Germany -
| Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
|---|---|---|---|---|---|---|---|
| Immediate | 11 Oct, 2024 | Not Specified | 12 Jul, 2024 | 9 year(s) or above | Functional Specifications,Cdc,Reporting,Lint,Iso,Pcie,Python,Fault Analysis,Rtl Development,Ee,Customer Requirements,Perl,Functional Safety,Rtl Coding,English | No | No |
Required Visa Status:
| Citizen | GC |
| US Citizen | Student Visa |
| H1B | CPT |
| OPT | H4 Spouse of H1B |
| GC Green Card |
Employment Type:
| Full Time | Part Time |
| Permanent | Independent - 1099 |
| Contract – W2 | C2H Independent |
| C2H W2 | Contract – Corp 2 Corp |
| Contract to Hire – Corp 2 Corp |
Description:
51159BR
GERMANY - Munich, GREAT BRITAIN - Edinburgh, GREAT BRITAIN - Reading, IRELAND - Dublin, IRELAND - Ireland, PORTUGAL - Porto, ROMANIA - Bucharest
WE’RE LOOKING FOR AN EXPERIENCED DIGITAL DESIGN ENGINEER TO JOIN OUR AUTOMOTIVE DIGITAL INTERFACE CONTROLLER IP TEAM.
The Automotive Digital Design Engineer is expected to:
- Be responsible for specification development, architecture design and RTL development of Automotive specific features / enhancements.
- Proactively develop safety mechanisms that can be embedded within our IP and reused easily
- Work closely with the verification team and review verification plan mapping with the specification.
- Work with product teams to evaluate customer requirements related to quality, functional safety, and automotive reliability.
- Work closely with the Functional Safety and internal development teams on projects and task planning, progress tracking and reporting.
Key Qualifications
- Must have BSEE in EE with 10+ years of relevant experience or MSEE with 9+ years of relevant experience.
- Must have proven experience working on Automotive SoC’s / Digital IP’s.
- Must have proven experience working of one or more of protocols at the IP level: DDR / PCIe / UCIe.
- Hands on experience with architecting / micro-architecture / detailed design from functional specifications.
- Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools.
- Lint, CDC, synthesis flow and static timing flows, formal checking, etc experience.
- Working knowledge / experience TCL, Perl, Python is added advantage.
- Has a strong desire to learn and explore new technologies.
- Performs in project leadership role & guides more junior peers with aspects of their job.
- Frequently networks with senior internal and external personnel in own area of expertise.
- Proficient in English.
- Formal training in ISO 26262 is preferred.
- Experience in qualifying systems with embedded hardware to various ISO 26262 ASIL levels up to ASIL D
- Experience with various ISO 26262 work products such as FMEA Analysis; FMEDA Analysis; Dependent Fault Analysis
Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:9.0Max:10.0 year(s)
Information Technology/IT
Engineering Design / R&D
Information Technology
Graduate
Proficient
1
München, Germany
