Defect & Yield Engineer / 6 months contract / Semiconductor/ Yishun

at  UNI CONNECT TECHNOLOGIES PTE LTD

Responsibilities:

• Responsible for yield improvement activities includes identifying, analyzing OOC lots, Defect Pareto, defect trend and characterization data to determine the source of defect.
• To work closely with module process/equipment engineers to formulate and implement robust technical improvement solutions for both excursions and baseline defect improvement.
• To work with AVI process engineer to improve defect detection for yield improvement activities.
• Send out periodic reports on process metrics.
• Support engineering LCO and MRB analysis

Requirements:

• Degree holder with 3-5 yrs experience. Semiconductor experience is preferred.
• Demonstrate knowledge and understanding of SPC and its applications in the area and knowledge of semiconductor equipment and processes.
• Demonstrate proactive problem solving, communicate openly, and take responsibility.
• Demonstrate the ability to troubleshoot problems to address root causes.

Interested candidates can send their resume to deepti@uniconnect.com.s

• Responsible for yield improvement activities includes identifying, analyzing OOC lots, Defect Pareto, defect trend and characterization data to determine the source of defect.
• To work closely with module process/equipment engineers to formulate and implement robust technical improvement solutions for both excursions and baseline defect improvement.
• To work with AVI process engineer to improve defect detection for yield improvement activities.
• Send out periodic reports on process metrics.
• Support engineering LCO and MRB analysi