Design Verification Engineer

at  Advanced Micro Devices Inc

PREFERRED SKILL SETS :

• Advanced knowledge of ASIC Design flow and state of the art verification flow
• Proficient with Verilog, System Verilog and UVM
• Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus
• Test bench creation and Test environments

EDUCATION :

• Major in EE, CS or related, Master Degree

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:
TITLE : Design Verification Engineer

THE ROLE :

In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. You will be leading IP functional verification tasks. This team also is responsible for the Design and Verification of several critical as well as the integration to other subsystems and SoC. The Design and Design Verification groups within this team are also responsible for developing a balanced architecture between power consumption and performance, delivering high complexity RTL code and creating sophisticated testbenches using groundbreaking verification techniques.

RESPONSIBILITIES:

Collaborate with design team to understand and define verification requirements for high-speed, low power digital circuit designs from definition to implementation. Own or be involved in all aspects of the functional verification from initial test planning, test creation and debug. to coverage and sign-off closure, while providing technical leadership to the team.
Own verification of high speed, low power digital designs at IP and System level using both coverage driven constraint random and directed testing techniques as well as formal verification. Implement test benches and components such as test and sequence libraries, monitors, models and BFMs by applying objected oriented programming verification techniques following UVM methodology.