Design Verification Engineer

at  Apple

SUMMARY

Posted: Oct 17, 2024
Weekly Hours: 40
Role Number:200573877
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. Dynamic, hard-working and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Apple is looking for a talented and motivated Design Verification to be part of a highly talented team.

DESCRIPTION

• You will collaborate with all disciplines (vertical product model) * You will ensure the quality of the SC or a IP or subsystem * You will review design and architecture specifications and work closely with micro-architecture teams * You will understand the functional & performance goals of the design and you use this knowledge to test effectively * You will develop test plans, tests and coverage plans as well as define Apples next generation verification methodology test benches * You will communicate and collaborate with design, architecture and software teams to understand the use cases and corner conditions and drive test cases * You will run and triage regressions, tracking bugs, and analyzing coverage to achieve top results

• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy

• Knowledge of Verilog/System Verilog, digital simulation and debug
• Knowledge of computer architecture and digital design fundamentals
• Ability to work independently to deliver the project goals
• Exposure to UVM is desired
• Experience with C/C++, assembly is a plus
• Experience with Perl, Python, or similar scripting language
• Strong problem solving and analytical skills
• Strong communication skills combined with team-oriented approaches to own the verification efforts

PREFERRED QUALIFICATIONS

• BSEE or BSCS required, Master’s or PhD desired

• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
• Knowledge of Verilog/System Verilog, digital simulation and debug
• Knowledge of computer architecture and digital design fundamentals
• Ability to work independently to deliver the project goals
• Exposure to UVM is desired
• Experience with C/C++, assembly is a plus
• Experience with Perl, Python, or similar scripting language
• Strong problem solving and analytical skills
• Strong communication skills combined with team-oriented approaches to own the verification effort