Design Verification Engineer
at NIVABIZ PTE LTD
Singapore, Southeast, Singapore -
| Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
|---|---|---|---|---|---|---|---|
| Immediate | 19 Nov, 2024 | USD 5000 Monthly | 22 Aug, 2024 | 5 year(s) or above | Code,Verilog,Analytical Skills,Vhdl,Completion | No | No |
Required Visa Status:
| Citizen | GC |
| US Citizen | Student Visa |
| H1B | CPT |
| OPT | H4 Spouse of H1B |
| GC Green Card |
Employment Type:
| Full Time | Part Time |
| Permanent | Independent - 1099 |
| Contract – W2 | C2H Independent |
| C2H W2 | Contract – Corp 2 Corp |
| Contract to Hire – Corp 2 Corp |
Description:
SKILLS:
Skilled in Verilog, System Verilog, UVM
Experience IP Level & SOC Level Verification.
High Experience in defining block, Sub-System and SOC top level test plans.
Experienced with System Verilog assertions, code and functional coverage implementation and analysis.
REQUIREMENTS
Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 5 year of experience
Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
Strong understanding of verification process from test plan to coverage completion
Strong communication and Analytical skills
Understanding of HDL (Verilog, VHDL)
Experience with one or more high speed protocols is an added advantage.
Interested applicants, kindly send in a copy of your resume stating your current and expected remuneration together with the notice period. Pls send you resume to business@nivabiz.com.s
How To Apply:
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Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:5.0Max:10.0 year(s)
Information Technology/IT
Engineering Design / R&D
Information Technology
Graduate
5 year of experience
Proficient
1
Singapore, Singapore
