Design Verification Engineer (Verilog)
at ALTROCKS TECH PTE LTD
Singapore, Southeast, Singapore -
| Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
|---|---|---|---|---|---|---|---|
| Immediate | 24 Oct, 2024 | USD 9000 Monthly | 25 Jul, 2024 | 5 year(s) or above | Code,Verilog,Communication Skills,Systemverilog | No | No |
Required Visa Status:
| Citizen | GC |
| US Citizen | Student Visa |
| H1B | CPT |
| OPT | H4 Spouse of H1B |
| GC Green Card |
Employment Type:
| Full Time | Part Time |
| Permanent | Independent - 1099 |
| Contract – W2 | C2H Independent |
| C2H W2 | Contract – Corp 2 Corp |
| Contract to Hire – Corp 2 Corp |
Description:
Experience: 5 years & above
- Experience IP Level & SOC Level Verification.
- Skilled in Verilog, SystemVerilog, UVM
- High Experience in defining block, Sub-System and SOC top level test plans.
- Experienced with System Verilog assertions, code and functional coverage implementation and analysis.
- Experience with one or more high speed protocols is an added advantage.
- Good interpersonal and communication skills
Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:5.0Max:10.0 year(s)
Information Technology/IT
IT Software - Other
Information Technology
Graduate
Proficient
1
Singapore, Singapore
