DFx Engineer

at  Advanced Micro Devices Inc

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (e.g. JTAG 1149.x, Scan, Memory BIST, PRBS, IO Loopback, etc.)
• Understanding of Design for Debug methodologies and DFD features verification experience (e.g., Debug bus, Tracing, Trigger, Logic Analyzer, etc.)
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
• Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization
• Experience in post-Si system level debug and use of tools such as JTAG debuggers, logic analyzers, and PCIe bus analyzers

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

We are looking for an adaptive, self-motivated DFx design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The NBIO DFx team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

KEY RESPONSIBILITIES:

• Verification of Analog/HSIO DFx architecture and features
• Build testbench components to support the next generation of NBIO IPs
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Develop, maintain and improve test libraries to support IP level testing
• Test coverage and test cost reduction analysis
• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning