Digital Design Engineer

at  XFAB Silicon Foundries

The X-FAB Group - about 4,000 employees - is the leading analog/mixed-signal foundry manufacturing silicon wafers for analog-digital integrated circuits (mixed-signal ICs). X-FAB customers benefit from high-performance technologies, excellent technical design and prototyping services; and fast, easy and flexible foundry access worldwide.

JOB SUMMARY

• You will be part of a team responsible in digital IP development including RAM, ROM and digital libraries. You will have the responsibility to specify and design digital Integrated Circuit embedding the developed digital IPs to allow their Silicon validation in the context of ISO26262 environment.

POSITION REQUIREMENTS

• Qualification: Master or higher in Electronics Engineering.
• Minimum 5 years of working experience in developing digital Integrated Circuit. Mandatory Back-End digital design skills (Place and Route, Physical Verification). Front-End digital design (RTL) is an advantage.
• Skills/Competencies:

Behavioral Competencies

• Good communication skills – good level in English, written and spoken.
• Teamwork and collaboration skills, working within multi-national, multi-site team
• Open, curious in new design implementation, new DFT methodology, integrity and friendly when engaging internal/external customers.
• Self-motivated, progressive attitude, and able to work independently with minimum supervision

Technical/ Functional Competencies

• Good knowledge and understanding of digital circuits
• Experience with Place and Route tool for floor planning, CTS and routing and Physical Verification (LVS, DRC)
• Timing Analysis and Power Analysis
• Synthesis and DFT insertion
• RTL design and verification experience is a plus
• Scripting (TCL, perl, python) for automatization

• Specifications of test chips allowing the silicon measurement of all parameters of RAM, ROM and digital libraries e.g., leakage current, power consumption, access time, peak current, … Propose design solution allowing the most accurate measurements.
• Develop digital Integrated Circuit including the full development flow RTL, Synthesis, DFT insertion, Place and Route, Physical Verification (DRC, LVS), RTL and gate level Simulation.
• Generate functional Test patterns e.g., ATPG and custom test patterns. Define by simulation limits for parametric tests with Static Timing Analysis reports, Power Analysis reports
• Evaluate new DFT methodology e.g., Cell-Aware Test patterns
• Documentation relative to Test Chips datasheet and test datasheet
• Interface with Test Engineers, organize debug session for issue analysis
• Contribute to QA flow for digital IP usage. Interface with digital IP designers. Report and document improvement for better digital IP integration/usage.
• Specify and design Test Qualification Vehicle for digital IP and technology process qualification and demonstrator to highlight the capability of the technology and digital IP portfolio.