Early career - SoC Physical Design STA / Timing Engineer (M, F, D)

at  Apple

SUMMARY

Posted: 25. Jul 2024
Role Number:200559263
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. Multifaceted, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the outstanding and exciting opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Join us! You will be taking part in the Physical Design team as a backend focal point for timing analysis and convergence, working in sophisticated technologies and interacting closely both with RTL designers, Physical Designers and other top level integration teams.

DESCRIPTION

Work with Physical Design team, highlighting issues & best practices. Help build timing ECO’s for project tapeout. Build/maintain scripts and methodologies for analysis and runs. You will be responsible for constraints and timing checkups development, including their delivery for synthesis, PnR and signoff STA. Working in parallel on blocks and chip level STA modes.

• Bachelors’s or Master’s Degree in a technical field is required.
• General knowledge of the ASIC design timing closure flow and methodology.

• Understanding of STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.Ability to fluently speak and write in English.

PREFERRED QUALIFICATIONS

• General knowledge in timing/SDC constraints generation and management.
• Proficient in scripting languages (TCL and Perl).
• Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
• Understand and implement improving existing methodologies and flows.
• Knowledge in constraint analysis and debug, using industry standard tools as well as backend STA closure is a plus.
• Familiar with ECO techniques and implementation.
• Some experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow.
• Familiar with hierarchical design approach, top-down design, timing and physical convergence.
• Good communication and interaction with Front End teams and Physical Design teams.

ADDITIONAL REQUIREMENTS

Meh

• Bachelors’s or Master’s Degree in a technical field is required.
• General knowledge of the ASIC design timing closure flow and methodology.
• Understanding of STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.Ability to fluently speak and write in English