Experienced ASIC Digital Verification Engineer

at  Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

EXPERIENCED ASIC DIGITAL VERIFICATION ENGINEER

Responsibilities

• Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification.
• Write test cases, checkers, and coverage that implement the verification test plan.

Job Requirements

• Bachelors or Masters with relevant digital verification experience in the industry
• Experience of verification of interfaces and controllers for high-speed serial protocols such as PCI-Express, CXL, or SAS/SATA
• RTL verification using coverage driven verification techniques
• Scripting in any language. Programming experience or coursework in C, C++
• Proficient in HDL languages System Verilog, Verilog, or VHDL
• Good analytical, oral, and written communication skills
• Self-motivated, proactive team player

Unique opportunities presented with this position

• To grow and manage verification of product end-to-end.
• Cross-functional learning and interaction with professional teams across domains and geographies.
• Customer-facing role working in close collaboration with pre and post-sales team
• Develop systematic ways to address new problems, think outside of the box
• Have an impact on the new product architectures, quality and development strategies

• Define verification plans and build verification environments for chip/module level designs using System Verilog with UVM.
• Apply advanced verification techniques like constrained random generation, functional coverage, assertions and formal verification.
• Write test cases, checkers, and coverage that implement the verification test plan