Formal Verification Engineer

at  Apple

Beaverton, Oregon, USA -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate29 Oct, 2024Not Specified29 Jul, 20243 year(s) or aboveApple,Affirmative Action,ColorNoNo
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Description:

SUMMARY

Posted: Jul 26, 2024
Role Number:200560664
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Work with the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly.

DESCRIPTION

As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: - Working with Apple Silicon’s world-class SOC and IP design engineers to develop a formal micro-architecture specification - Developing comprehensive formal verification test plan - Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture - Crafting novel and creative solutions for verifying complex design micro-architectures - Developing and implementing re-usable and optimized formal models and verification code base - Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

  • A minimum of a bachelor’s degree and a minimum of 3 years of relevant industry experience in silicon validation software engineering or related field.

PREFERRED QUALIFICATIONS

  • Expert in SoC, CPU, GPU, and/or Cellular designs, as well as VLSI and digital logic design and verification techniques, or expert in formal tools and methodology and their application in and industrial setting
  • Detail oriented mindset and desire to overcome challenges.

ADDITIONAL REQUIREMENTS

More

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Responsibilities:

  • A minimum of a bachelor’s degree and a minimum of 3 years of relevant industry experience in silicon validation software engineering or related field


REQUIREMENT SUMMARY

Min:3.0Max:8.0 year(s)

Information Technology/IT

Engineering Design / R&D

Software Engineering

Graduate

Silicon validation software engineering or related field

Proficient

1

Beaverton, OR, USA