FPGA Designer
at Expleo Group
1000 Brussels, Brussel-Hoofdstad - Bruxelles-Capitale, Belgium -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 16 Dec, 2024 | Not Specified | 17 Sep, 2024 | N/A | C,Python,Writing,C++,Computer Science,Subversion,Synplify,Software Development | No | No |
Required Visa Status:
Citizen | GC |
US Citizen | Student Visa |
H1B | CPT |
OPT | H4 Spouse of H1B |
GC Green Card |
Employment Type:
Full Time | Part Time |
Permanent | Independent - 1099 |
Contract – W2 | C2H Independent |
C2H W2 | Contract – Corp 2 Corp |
Contract to Hire – Corp 2 Corp |
Description:
3. REQUIREMENTS:
We are not looking for the candidate that ticks all the boxes, but if you find yourself in the following sentences then we would be glad to have a chat with you!
- 5+years’ experience in software development
- Engineering degree in computer science, system engineering or comparable
- Experience in reading, writing, defining, and implementing test specifications
- Ability to code in C, C++, or Python
- Knowledge of IT infrastructure technology (networking, operating systems, cybersecurity)
- Experience in Modelsim/Questasim (FPGA simulation)
- Experience in Synplify (FPGA synthesis)
- Experience in SubVersion (FPGA configuration control)
- Familiar with Agile methodology
Responsibilities:
You will be working in a team that develops and test critical software applications.
- Ability to draft a FPGA architecture and design starting from FPGA requirements and an earlyconceptual design
- Ability to follow completely the ECSS-E-ST-20-40C and ECSS-Q-ST-60-03C requirements(development flow, documentation requirements)
- Experience with Microchip devices (preferably RTAX and RTG4 family)
- Experience with ProAsic devices (used for prototype development)
- Ability to code the design in VHDL in a structured manner – focus on re-use
- Ability to perform simulations with ModelSim
- Ability to achieve 100% statement and branch coverage
- Ability to achieve 100% FEC coverage (Focussed Expression Coverage) TBD
- Ability to correctly check CDC (Clock Domain Crossings)
- Ability to assist in integrating a FPGA design (mapping of schematic signal names onto VHDLsignal names –SCHEMA2FPGA file)
- Ability to achieve static and dynamic timing closure
- Ability to create the correct synthesis constraints
- Ability to perform post layout timing simulations
- Ability to prepare the test specification matrix
- Ability to fully document the design (including design justification, results of analysis, see ECSSfor all documentation
REQUIREMENT SUMMARY
Min:N/AMax:5.0 year(s)
Information Technology/IT
IT Software - System Programming
Information Technology
Graduate
Computer Science, Engineering
Proficient
1
1000 Brussels, Belgium