JOB DESCRIPTION

Join Intel to have an opportunity to create and extend computing technology to connect and enrich the lives of every person on Earth. In this role you’ll supervise a team of DTCO (Design Technology Co-Optimization) engineer performing all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create an optimal design.

As DTCO APR engineer(Graduate Talent), your responsibilities include although not limited to:

• Support RTL synthesis and place and route experiments using internal and external vendor tools to improve Intel’s product Power, Performance, and Area, for existing and future process nodes on internal Intel Architecture (IA/X86) and external ARM IP’s.
• Deal with changes in floorplan, corresponding scaling, and its impact to power, congestion, and timing for the present technology node and predict how it would impact the scaling of power, routing and timing for the next technology node.
• Help improve cell utilization and transistor density metrics by leveraging leading edge tools and methodologies.
• Able to analyze power (dynamic and leakage), performance (setup and hold), improve critical path timing, find ways to reduce congestion by making best use of available metal layers, debug tools and more.

QUALIFICATIONS

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• You should have Bachelor/Master in Electrical or Electronic Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field.
• Proficient in TCL, Perl or Python programming language.

Preferred Qualifications:

• Ability to work in a fast-paced, collaborative, and often intense project schedule.
• Excellent communication and interpersonal skills, a good team-player as well as able to work independently.
• Possess creative mind and self-motivated.
• Analytical problem solving and multitasking.
• Able to do pathfinding or research independently to find solutions.

DesignEnablement

• Support RTL synthesis and place and route experiments using internal and external vendor tools to improve Intel’s product Power, Performance, and Area, for existing and future process nodes on internal Intel Architecture (IA/X86) and external ARM IP’s.
• Deal with changes in floorplan, corresponding scaling, and its impact to power, congestion, and timing for the present technology node and predict how it would impact the scaling of power, routing and timing for the next technology node.
• Help improve cell utilization and transistor density metrics by leveraging leading edge tools and methodologies.
• Able to analyze power (dynamic and leakage), performance (setup and hold), improve critical path timing, find ways to reduce congestion by making best use of available metal layers, debug tools and more