JOB DESCRIPTION

This position is within the Design Enablement (DE) organization of Technology Development.
At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel’s most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers.
The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.

Runset Development:

• Runset Development team within this organization is to develop physical layout verification software (DRC, LVS, RC extraction) and support the latest Intel technologies and microprocessor designs.
• Develop runset using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus).
• Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders.
• Support PDK development and Intel design teams to debug and enhance runset quality and enhance runtime and usability of the runset.

Custom Layout Kits Development:

• L0 or development quality assurance of custom layout EDA technology files and/or primitive libraries and other custom collateral used by industry standard custom design and layout for various Intel process nodes.
• Develop automation software and scripts for generation and validation of Process Design Kit (PDK) collaterals and analysis of CAD tool results.
• Develop Custom Layout tools and Technology file development (Virtuoso or Custom Compiler)
• Experience in Layout of analog, RF, or digital circuits on advanced process technology nodes.
• Experience with industry standard CAD tools for schematic entry and/or custom layout from vendors such as Cadence, Synopsys, and Siemens.

Extraction Development:

• Understand and model parasitic related to the interconnects.
• Work with multiple EDA companies to co-develop extraction solutions.
• Develop new extraction techniques to address upcoming technology features not yet handled in existing industry extraction tools and validates EDA solutions against models and measured data.
• Extraction runset and flow development using popular extraction solutions (StarRC, Quantus, xACT)
• Work with various solvers (e.g. Raphael, HFSS, Fast Henry, Quick Cap, university-developed tools) and popular 2D and 3D electromagnetic packages.

QUALIFICATIONS

The candidate must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork class research and or relevant previous job and or internship experiences.

Minimum Qualifications:

• You should have Bachelor or Master in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field.
• Proficient in TCL, Perl or Python programming language.
• Unix/Linux operating system

Preferred Qualifications:

• Ability to work in a fast-paced, collaborative, and often intense project schedule.
• Excellent communication and interpersonal skills, a good team-player as well as able to work independently.
• Creative mind and self-motivated.
• Analytical problem solving and multitasking.
• Able to do pathfinding or research independently to find solutions.

designenablement

Please refer the Job description for details