Graphics FE Implementation Engineer

at  Apple

SUMMARY

Posted: Aug 16, 2024
Role Number:200563996
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!

DESCRIPTION

You will be responsible for PPA optimization of the netlist, working closely with the RTL and Physical design teams. You will also deliver key netlist quality achievements for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.

• We are looking for candidates with experience with physical synthesis, including logic and PPA optimization techniques.
• Understanding and application of physical design and static timing analysis principles.
• Proficient in Verilog and/or System Verilog and scripting languages.
• Ability to analyze critical paths and guide RTL designs to optimal solutions.
• Experience using logic equivalence tools for RTL and Gate-level designs.
• Minimum of BS + 3 years of experience.

PREFERRED QUALIFICATIONS

• Familiarity with DFT insertion.
• Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
• Experience implementing ECOs for functionality and timing.
• Collaborate effectively with IP teams spanning multiple sites.

• We are looking for candidates with experience with physical synthesis, including logic and PPA optimization techniques.
• Understanding and application of physical design and static timing analysis principles.
• Proficient in Verilog and/or System Verilog and scripting languages.
• Ability to analyze critical paths and guide RTL designs to optimal solutions.
• Experience using logic equivalence tools for RTL and Gate-level designs.
• Minimum of BS + 3 years of experience