Hardware Engineering Architect

at  Cisco Systems

The application window is expected to close on February 28, 2025
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Preference will be given to candidates located in the Bay area who can work onsite at our San Jose office three days a week. Alternatively, we welcome applications from candidates who can work remotely from within the USA.
Candidates outside the San Jose area may be required to travel 5-10% of the time to the San Jose office.

MINIMUM QUALIFICATIONS:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related disciplines with 10+ years in ASIC development
• 5+ years’ experience with digital design.
• 5+ years’ experience with ASIC architecture
• Experience with networking protocols like Ethernet, IP, MPLS, VxLAN, and more.

PREFERRED QUALIFICATIONS:

• Experience with modeling and simulation, particularly for digital hardware systems
• Experience with TLM (Transaction-Level Modeling) and other modeling standards.
• Experience with C++ or System C.
• Collaborative mindset, with meticulous attention to detail and problem-solving abilities.
• Familiarity with design verification concepts and methodologies

Please refer the Job description for details