Hardware Modeling Engineer

at  Cisco Systems

The application window is expected to close on February 28, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
We prefer candidates who can work onsite at our San Jose office three days a week. Alternatively, we are open to considering candidates who can work remotely from within the USA, with a preference for those in the EST time zone.
Candidates outside the San Jose area may be required to travel 5-10% of the time to the San Jose office.

MINIMUM QUALIFICATIONS:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related disciplines with 5+ years in ASIC or chip development-related engineering.
• Experience in modeling and simulation, particularly for digital hardware systems.
• Experience in C++ with strong object-oriented programming skills.

PREFERRED QUALIFICATIONS:

• Experience with TLM (Transaction-Level Modeling) and other modeling standards.
• Familiarity with digital design and HDLs such as Verilog or VHDL.
• Strong technical communication and documentation skills.
• Collaborative approach, with meticulous attention to detail and problem-solving abilities.
• Familiarity with networking protocols
• Familiarity with design verification concepts and methodologies
• Experience in scripting languages, such as Python or Perl

Please refer the Job description for details