NAND Packaging Engineer

at  Apple

SUMMARY

Posted: Oct 3, 2023
Role Number:200450101
Envision what you could do here. At Apple, we believe new ideas and insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight, and inspire millions of Apple’s customers every single day. SEG Packaging is a key part of the HW Technology team. This team invents, designs, develops and integrates electronic packaging solutions for the Apple’s internal and customized external components of hardware for its consumer electronic products. As a NAND packaging engineer, you will lead the memory package development by managing the external memory vendors and steering their packaging design compatibility to Apple system components. You will partner with other cross functional teams, defining the memory package architecture, die pad layout, package form factor, interconnect and package density, and will support the system and product teams and overall program through the development and NPI cycle.

DESCRIPTION

Define the memory package POR (plan of record): Package architecture, technology, process, form factor, layout, bill of materials (BOM), design rules, thermo-mechanical, signal integrity, power integrity Publish internal package specs for customized memory Establish trusting and collaborative relationships and communication channels, as a direct interface with vendors for memory package development and qualification Review, drive, and approve memory vendor DOEs, characterization plans, technology and product qualification Drive industry with advanced package design rules, processes, materials, and leading-edge specifications About 10% international travel required

KEY QUALIFICATIONS

• We are looking for someone with 2+ years’ experience in package design and assembly process development for stacked-die memory packages
• Strong knowledge of wirebond and flip-chip assembly process applied to thin-die stacking
• Strong knowledge of packaging materials, substrate technology, and their mechanical and thermal behaviors
• Working knowledge of assembly design rules, SIPI, and layout tradeoffs to enable high performance DDR or differential signaling
• Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology
• Excellent engineering problem solving skills, with strong engineering physics and data driven analysis
• Strong written and verbal communication skills for working with internal multi-functional teams and OSATs

EDUCATION & EXPERIENCE

BS and 3+ years of relevant industry experience

Please refer the Job description for details