Physical Synthesis CAD Engineer

at  Apple

SUMMARY

Posted: Sep 19, 2024
Role Number:200567799
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!

DESCRIPTION

You will apply your hand-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. Primary Responsibilities will include: - Develop and improve existing flows for Physical Synthesis and DFT Implementation - Support multiple design teams and work with cross functional teams to solve key physical synthesis challenges - Collaborate with other flows like Logic Equivalence, Static Timing Analysis and Low Power (UPF) Implementation - Work with tool vendors to resolve tool/flow issues

• Experience with TCL, Python or Perl scripting languages
• Knowledge of Logic design fundamentals
• Experience with Synthesizable System Verilog RTL
• Minimum requirement of BS + 0 years of relevant industry experience

PREFERRED QUALIFICATIONS

• Knowledge or experience with industry standard Logic Synthesis tools like Fusion Compiler or Genus
• Exposure to static timing analysis and logic equivalence tools
• Experience with writing synthesizable RTL code
• Proficiency with TCL, Python or Perl scripting languages strongly preferred

• Experience with TCL, Python or Perl scripting languages
• Knowledge of Logic design fundamentals
• Experience with Synthesizable System Verilog RTL
• Minimum requirement of BS + 0 years of relevant industry experienc