PMU Design Verification Engineer (m/f/d)

at  Apple

SUMMARY

Posted: 21. Aug 2024
Role Number:200559252
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique and exciting opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will involve verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

DESCRIPTION

As a part of a highly dedicated team you will be at the core of our chip design efforts. You will develop and execute verification plans in coordination with design leads and architects. Your responsibilities will include: - Actively participating in building and maintaining the verification infrastructure including test bench components, environments, test cases, ensuring scalability and portability across various projects - Defining the verification strategy (constraint random, formal, directed etc.) for digital and mixed-signal IP/Subsystem and SoC verification - Actively participating in cross functional collaboration with design teams to ensure a successful product delivery Thanks to our unique PMU architecture, you will be exposed to cutting-edge technology from both the digital and analog domains. You will not only participate in chip verification, but you will also have the opportunity to develop your own skills, fostering your expertise in the field.

• BSc in CS, EE or equivalent field or equivalent work experienceFluent communication skills in English

PREFERRED QUALIFICATIONS

• Experience in developing verification infrastructure for complex digital or mixed-signal IPs/Sub-systems or SoCs, including development of test cases, scoreboard, SystemVerilog Assertions
• Good understanding of verification methodology, preferably UVM
• Basic knowledge of digital and mixed-signal design
• Experience with C/C++ is a plusExcellent communication and interpersonal skills, combined with the ability to collaborate

ADDITIONAL REQUIREMENTS

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• BSc in CS, EE or equivalent field or equivalent work experienceFluent communication skills in Englis