Principal Design Verification Engineer

at  Analog Devices

Edinburgh, Scotland, United Kingdom -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate31 Jan, 2025Not Specified01 Nov, 202410 year(s) or aboveVerilog,Verilog Ams,Utilities,Scripting Languages,Python,Perl,Communication Skills,Formal Verification,ClosureNoNo
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Description:

Responsibilities:

Please refer the Job description for details


REQUIREMENT SUMMARY

Min:10.0Max:15.0 year(s)

Information Technology/IT

IT Software - System Programming

Information Technology

Graduate

Verification

Proficient

1

Edinburgh, United Kingdom