Principal Digital Modelling and Design Engineer (f/m/d)

at  NXP Semiconductors

READY TO JOIN THE FUTURE OF INNOVATION IN DIGITAL DESIGN ENGINEERING?

This opening is within the Advanced Chip Engineering (ACE) SoC Implementation Organization, a central R&D Design group responsible for end-to-end IC/SoC implementation of the Automotive and Industrial Automation Processors in NXP.
We are seeking a Principal Digital Modelling and Design Engineer (f/m/d) to join our team in Hamburg, Germany. The Hamburg SoC integration team develops complete “System on Chip” products in the domain of Radar applications and Radio Infotainment. International relocation can be accommodated for qualified candidates.

• Design, modelling and elaboration of abstractions that enable pre-silicon simulations of HW design using industry CAD tools
• Creation of HW, IC/IP and SoC models using SystemC that enable early SW prototyping
• Programming in Matlab/Simulink: Modelling and abstraction of HW IC/IP from architectural concepts and/or requirements
• FPGA tooling, design and verification: Creation of HW models from early RTL that enable early development
• Automation using scripting languages like Python or Perl
• Analysis, comparison and selection of different circuit topologies for optimal design: Ability to generate models and early RTL using CAD tools
• Contributing to micro-architecture, RTL design and integration of a System on Chip (SoC) or SoC sub-system, from requirements specification to tape-out and beyond
• Working with different functions like architecture, verification, DFT, physical implementation, post-silicon validation, etc. to provide early models that enable earlier progress
• Ability to create models for digital circuits that include the following areas:
• Digital signal processing IPs: filters, mixers, state machines, etc.
• Clock and reset infrastructure
• On-chip interconnect and interfaces
• ARM CPU/MCU and DSP architectures
• Design for low power and UPF modelling
• Communication/control peripherals like PCIe, USB, DDR
• AMS circuits and IPs including PLLs, receivers, transmitters, LDOs, amplifiers, mixersetc
• Develop and deliver signed-off verilog RTL and associated deliverables (e.g. clock/reset domain constraints, timing constraints, design documentation)
• Performance, power, area and timing optimizations of your design following requirements and other constrains established by IC SoC Product architects
• Resolve design problems using knowledge of several of the following areas:
• Digital signal processing architecture and design
• Clock and reset infrastructure
• On-chip interconnect and interfaces
• ARM CPU/MCU and DSP architectures
• Design for low power and UPF modelling
• Communication/control peripherals like PCIe, USB, DDR