ABOUT CELESTIAL AI

With the growth in Generative AI, data center infrastructure it is not just about the System on Chip but about the System of Chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric is the next-generation interconnect technology offering a10X increase in performance and energy efficiency over competitive technologies.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This enables our customers to seamlessly integrate high bandwidth, low power, low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging flows. This ease of integration enables XPUs to have optical interconnects for compute-to-compute and compute-to-memory fabrics that deliver tens of Tbps bandwidth with nano-second latencies.
This innovation empowers hyperscalers to improve the efficiency and economics of AI processing by optimizing the XPUs needed for training and inference and significantly lowering the TCO2 impact. To support customer engagements, Celestial AI is cultivating a Photonic Fabric ecosystem. These tier-1 partnerships consist of custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

JOB DESCRIPTION

In this role, you join a world-class analog team designing high performance analog and mixed mode circuits. You will leverage your deep knowledge and experience in analog design to provide technical, cross-functional leadership, partnering with Systems, Analog and Digital teams to architect and design circuits for high performance transceivers and other critical analog functions. This role requires a candidate with strong communication and collaboration skills, as key responsibilities include interfacing across the internal Celestial AI teams as well as externally with customers and partners.

QUALIFICATIONS

• Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 8+ years of experience.
• Proficiency with:
• Analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.)
• Analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• System level pre-tape out analog validation
• Lab chip bring-up and debugging efforts
• Knowledge of:
• Electromagnetic tools and extraction
• Fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution
• Analog layouts in FinFet and its effect on high-speed designs
• Strong communication and documentation skills
  Location: Toronto, Ontario, Canada
  As an early startup experiencing explosive growth, we offer an attractive total compensation package, inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The base salary range for this position is 199,000 CAD - 230,000 CAD. The range displayed reflects the minimum and maximum target salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
  We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
  Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
  

  LI-Onsit

• Design, Analog design of high-speed and high-performance SerDes in advanced technology nodes, 5nm, 3nm and beyond
• Work closely with System, Analog and Digital design teams for SerDes Architecture Development
• Develop AE/validation for the IP characterization and validation plan
• Support customers and partners
• Provide guidance and directive to layout engineers