Principal Engineer, HBM Design

at  Micron

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

OUR OPPORTUNITY SUMMARY:

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.
We are looking for a strong candidate to become a Principal level Engineer which focuses on HBM Design. Are you passionate about systems and architecture for the next generation of high-performance memory that has wide-ranging applications and inspires change in memory systems? In the HBM Design Engineering team at Micron, we deliver novel solutions to increase bandwidth, and capacity and reduce latency across memory and storage solutions.
You will be part of a highly multi-functional team of technical domain experts collaborating closely with a worldwide team of Design Engineering, Product Engineering, Process Development, Package Engineering, and our Business Units to implement a common goal of ensuring our future HBM roadmap is successful. You will apply your deep understanding of memory array architectures, high-speed interface design, logic & custom circuit design, memory subsystem operation, high-performance computing architectures, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative architectures to target best-in-class performance, power, cost, reliability and quality for Micron’s HBM product portfolio. The seniority level offered will be based on the combination of experience and education.
In HBM DEG (High Bandwidth Memory - DRAM Engineering Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, “high bandwidth”; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most challenging due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.
Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.

What’s Encouraged Daily:

• Collaborate with the architecture team and external customers on new product specifications
• Pathfinding to explore new system-level solutions for future HBM products and make recommendations after performing highly technical feasibility analyses
• Drive interface logic chip and memory architecture solutions
• Develop circuit designs for the memory array, input buffer, output buffer, control logic, address decode, datapath, internal test logic, power generators, PLL
• Chip in experienced knowledge to advance innovative technical solutions
• Provide advice and counsel to senior management on significant technical issues
• Coordinate and lead the layout process, including placement and routing optimization
• Contribute to cross-group communication to work towards standardization and group success
• Proactively solicit feedback from Standards, CAD, modeling, and verification groups to ensure the design quality
• Drive innovation into the future Memory generations within a dynamic work environment

HOW TO QUALIFY:

• MSEE or Greater
• 6+ years of relevant job/skill-related experience
• Experience delivering highly technical solutions
• In-depth technical expertise in one or more areas - DRAM memory array design, high-speed clocking and interface development, analog circuit design, digital/logic and custom circuit design, power delivery optimization, CMOS & semiconductor device physics, 2.5D and 3D packaging technologies

Please refer the Job description for details