Principal SoC DFT Design Engineer (f/m/d)

at  NXP Semiconductors

Ready to join the future of IC SoC design and innovation in DFT?
This opening is within the Microprocessor and Microcontroller Engineering (MME) organization, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design.
We are seeking a principal DFT Design Engineer to join our team in Hamburg, Germany. The Hamburg SoC integration team develops complete “System on Chip” products in the domain of Radar applications and Radio Infotainment products.
International relocation possibilities are available for qualified candidates.

KEY SOFT SKILLS

• Good communicator and collaborator, able to see things from the other person’s point of view.
• Willing to take up new challenges in the project and a good team player.
• Can demonstrate emotional intelligence and ability to work well as a part of local and international teams.

EDUCATION & SENIORITY

• M.Sc. Degree in Electrical Engineering or Computer Science
• Minimum of 5+ years of experience in DFT design and verification, with a focus on test pattern development.
  NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
  More information about NXP in Germany..

YOUR RESPONSIBILITIES:

• Collaborate in defining the Design for Testability (DFT) features and architecture for sophisticated System on Chip (SoC) designs ( RADAR, Infotainment products)
• Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs.
• Develop DFT logic and circuits, encompassing Serial Access Non-Destructive Testing (SCAN), Boundary SCAN, Memory Built-In Self-Test (MBIST), L-BIST and Analog Macro test logic and post-silicon support.
• Analyze Scan DRC reports and fixing DRC errors.
• Analyze ATPG reports on coverage and devise mechanism to improve coverage & generating patterns for ATE.
• Drive Power Aware RTL/GLS simulation bring-up and setting up regression suite for both Non-ATPG & ATPG needs.
• Create and manage DFT-related timing constraints, assisting backend engineers in achieving timing closure.
• Oversee the generation of DFT test patterns, as well as their simulation and debugging processes.
• Bring up Patterns on Wafer probe and on Final Test by working closely with Product & Test teams.

To be successful in this role you must have:

• Strong understanding of DFT methodologies, including Scan/Automatic Test Pattern Generation (ATPG), MBIST, L-BIST and Boundary Scan.
• Familiarity with DFT architectures such as JTAG, Scan compression techniques, scan chain insertion, built-in self-testing and verification, as well as analog testing strategies.
• Proficient understanding of digital SoC design principles, including Static Timing Analysis (STA) and verification,
• Mastery of hardware description languages, particularly Verilog, and Register Transfer Level (RTL) coding.
• Demonstrated commitment to meeting project schedules and maintaining high-quality work standards, with a strong team-oriented approach.
• Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
• Fluency in English language