Project Engineering Manager – PHY

at  Synopsys

Porto, Norte, Portugal -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate30 Nov, 2024Not Specified02 Sep, 2024N/ASecurity,Interfaces,Artificial Intelligence,Ms Project,Operating Systems,Color,Communication Skills,Processors,Project Plans,Specifications,It,JiraNoNo
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Description:

JOB DESCRIPTION AND REQUIREMENTS

As Project Engineering Manager you will manage mixed-signal IP projects, write specifications, review planning and participate on design tasks as required.
The successful candidate will work on a variety of management, documentation tasks and may also be involved in design and/or verification tasks.

Responsibilities:

  • Participate in complex block and/or chip planning and architecture studies.
  • Create clear project scope documentation and milestone definitions
  • Convene project kick-off and regular milestones tracking meetings with cross-functional teams
  • Maintain project plans and resource reports
  • Participate in design reviews and ensure that all quality checks are completed
  • Coordinate the production of IP Test Chips
  • Review silicon characterization reports, and design verification reports
  • Define and co-ordinate IP product releases
  • Manage product updates triggered silicon process updates, design updates, and customer feedback
  • Coordinate R&D team feedback during pre-sales customer engagements and review statements of work
  • Communicate with customers about technical issues
  • Work toward improving design efficiency and achieving highest possible quality metrics

Requirements:

  • Requires a degree in Engineering or Applied Science (or equivalent)
  • Requires 5+ years of experience in a customer facing and/or project management role
  • Familiarity with Project Management and Planning tasks
  • Familiarity with UNIX operating systems, Jira, MS Project and MS Excel
  • Good written and verbal communication skills
  • Solid organizational skills
  • Familiarity with the development process for ASIC designs.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market with reduced risk.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Responsibilities:

  • Participate in complex block and/or chip planning and architecture studies.
  • Create clear project scope documentation and milestone definitions
  • Convene project kick-off and regular milestones tracking meetings with cross-functional teams
  • Maintain project plans and resource reports
  • Participate in design reviews and ensure that all quality checks are completed
  • Coordinate the production of IP Test Chips
  • Review silicon characterization reports, and design verification reports
  • Define and co-ordinate IP product releases
  • Manage product updates triggered silicon process updates, design updates, and customer feedback
  • Coordinate R&D team feedback during pre-sales customer engagements and review statements of work
  • Communicate with customers about technical issues
  • Work toward improving design efficiency and achieving highest possible quality metric


REQUIREMENT SUMMARY

Min:N/AMax:5.0 year(s)

Information Technology/IT

Engineering Design / R&D

Information Technology

Graduate

Applied Science, Engineering

Proficient

1

Porto, Portugal