R&D Senior Staff Engineer - Design Verification (SystemVerilog-UVM)

at  SEARCH STAFFING SERVICES PTE LTD

Our client is a leading startup in the semiconductor field and a leader in designing ultra low-power microprocessors. The Singapore office houses the Regional Technology Design Center which will be driving the growth and innovation for its products.

REQUIREMENTS

• Bachelor’s or Master’s in Electrical Engineering, with 8-12 years of proven experience in block, sub-system, and full-chip verification.
• Disciplined, quality-minded, and highly driven for excellence.
• Expertise in understanding multiple architectures, integrating third-party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges.
• Strong proficiency in System Verilog simulation and C-based verification in an SoC environment.
• Extensive understanding and exposure to design verification for low-power, battery-operated designs.
• Familiarity with ARM processor-based designs and low-power design techniques (preferred).
• Mastery of System Verilog (UVM), Verilog, C/C++, Perl, Python, and Makefile.
• Experience with ARM SoC (preferred), AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, and QoS is required.
• Exposure to AI Edge inference, ISP, Video Codec, Video Processing, Audio Processing, MIPI (CSI/DSI), Crypto, OTP, DSP, and Low-Power technologies (preferred).
  Interested applicants, kindly send in a copy of your updated resume in WORD document to hr@searchstaffing.com.sg stating your current and expected remuneration together with notice period required to current employer.
  You can also contact Vincent Low for a confidential discussion at 6749 4236.
  EA Personnel Registration No: R132470

• Craft test plans to construct robust testbench environments using System Verilog and the Universal Verification Methodology (UVM).
• Integrate third-party VIPs, automate the test environment for efficient boarding, and leverage your in-depth knowledge of SoC architectures, including AMBA AXI/AHB/APB protocols, DMAs, security mechanisms, clock management, and power-gating techniques.
• Develop cutting-edge drivers, monitors, predictors, and scoreboards using UVM, ensuring comprehensive verification coverage and functionality validation.
• Craft innovative tests to evaluate power and performance aspects, guaranteeing optimal efficiency and real-world reliability.
• Collaborate with cross-functional teams to perform gate-level simulations and support FPGA and post-silicon bring-up, ensuring a seamless transition from design to deployment.
• Continuously enhance productivity by developing support utilities for verification automation, testbench automation, and regression testing.