Research Assistant in Power Amplifier Design for Hardware-in-the-Loop Simul

at  Imperial College London

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WHAT WE ARE LOOKING FOR

We are looking for candidates with the following skill sets:

• Detailed experience in power amplifier design based on SiC devices.
• Strong skills in high-power (>100 kW) PCB design and testing.
• Strong skills in Verilog and C coding for real-time control.
• Deep knowledge in analogue and digital circuits for power-electronic applications.
• Ability to write control code for embedded systems

FURTHER INFORMATION

The post is available from 01 Feb 2025 for up to 12 months. The post is based in the Department of Electrical and Electronic Engineering at Imperial College London (South Kensington Campus) working with Prof Tim Green and Dr Yunjie Gu. If you require any further details on the role please contact Dr Yunjie Gu yunjie.gu@imperial.ac.uk.
To apply, please click the button at the top of the page. Please ensure you include a completed application form with your submission.
Further information about the post is available in the job description.
Closing date: midnight on 9 February 2025

AVAILABLE DOCUMENTS

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ABOUT THE ROLE

Applications are invited for a Research Assistant within the Control and Power Research Group for research on four-quadrant high-bandwidth high-power amplifier for power-hardware-in-the-loop (PHIL) simulation. The Research Assistant will design and prototype the power amplifier including its power stack, modulation system and control system. Collaboration with other researchers in the lab is expected in order to integrate the power amplifier into the PHIL simulation system.

WHAT YOU WOULD BE DOING

You will be responsible for design of a hybrid silicon / silicon-carbide 3-level inverter capable of achieving a high switching frequency and high fidelity control of the voltage or current output. You will take forward the design into a build and test phase where integration with a real-time simulation environment is an essential objective. This will create a power hardware-in-the-loop test facility that upgrades our existing facility with higher performance and provide a research tool for use by the group. The work will require research into how to overcome hardware and software constraints on existing performance.