RTL Design Engineer

at  AMD

Job Description

PREFERRED EXPERIENCE:

Strong ASIC design experience is preferred
Proven RTL design experience on large ASIC development projects
Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
Strong background in Verilog and System Verilog
Strong analytical skills and attention to detail
Excellent written and communication skills
Understanding of the IP integration and interactions within an SOC
Must be a self-starter and able to independently drive tasks to completion
Demonstrates the ability to debug issues and quickly identify viable solutions
Team player with proven leadership skills

ACADEMIC EXPERIENCE:

Bachelor/ Masters of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_

THE ROLE:

The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution.

KEY RESPONSIBILITIES:

Understand the functional and performance requirements of the IOHUB within various SOCs
Drive IP/SOC design infra decisions to ensure consumption within the context of the SOC.
Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues
Scope requirements and resources to meet project schedules
Provide hands on leadership of a small team of Engineers/Engineers in Training as required to meet program development goals
Signoff IP quality for delivery into SOC
Effectively communicate with multi-disciplined teams located across the globe
Gather, attend and present into technical status meetings on a weekly/bi-weekly basis