Security ASIC Digital Design, Sr Engineer
at Synopsys
Porto, Norte, Portugal -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 26 Jan, 2025 | Not Specified | 26 Oct, 2024 | 2 year(s) or above | Verilog,Processors,Artificial Intelligence,Computer Science,Security,Interfaces | No | No |
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US Citizen | Student Visa |
H1B | CPT |
OPT | H4 Spouse of H1B |
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Employment Type:
Full Time | Part Time |
Permanent | Independent - 1099 |
Contract – W2 | C2H Independent |
C2H W2 | Contract – Corp 2 Corp |
Contract to Hire – Corp 2 Corp |
Description:
AT SYNOPSYS, WE’RE AT THE HEART OF THE INNOVATIONS THAT CHANGE THE WAY WE WORK AND PLAY. SELF-DRIVING CARS. ARTIFICIAL INTELLIGENCE. THE CLOUD. 5G. THE INTERNET OF THINGS. THESE BREAKTHROUGHS ARE USHERING IN THE ERA OF SMART EVERYTHING. AND WE’RE POWERING IT ALL WITH THE WORLD’S MOST ADVANCED TECHNOLOGIES FOR CHIP DESIGN AND SOFTWARE SECURITY. IF YOU SHARE OUR PASSION FOR INNOVATION, WE WANT TO MEET YOU.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
SECURITY DIGITAL DESIGN AND VERIFICATION ENGINEER
For the Security IP team in Porto, we are looking for a digital design and verification engineer who will work in state-of-the-art IP cores and subsystems to extend the Security IP business, in the markets of (HPC) High Performance Computing, (AI) Artificial Intelligence and Automotive. In this role you would:
- Architecture and design RTL in Verilog and System Verilog;
- Architecture and design test environments for digital hardware Security IP cores and complex subsystems, in System Verilog and UVM;
- Hardware verification of IP cores and subsystems with modern verification techniques like UVM or formal verification
- In cooperation with hardware and software security experts, perform functional and performance analysis of embedded hardware/software IP solutions;
- Work in an international team setup;
KEY QUALIFICATIONS
- RTL design expertise of hardware IP components;
- ASIC verification skills (using System Verilog, UVM, Verilog);
- Ability to create test environments specifications;
- MSc or PhD in Electrical Engineering or Computer Science;
- 2 years of relevant experience;
- Good knowledge about IC Design flows and excellent problem solving and debugging skills;
- Strong communication (written and verbal) and interpersonal skills.
Responsibilities:
- Architecture and design RTL in Verilog and System Verilog;
- Architecture and design test environments for digital hardware Security IP cores and complex subsystems, in System Verilog and UVM;
- Hardware verification of IP cores and subsystems with modern verification techniques like UVM or formal verification
- In cooperation with hardware and software security experts, perform functional and performance analysis of embedded hardware/software IP solutions;
- Work in an international team setup
REQUIREMENT SUMMARY
Min:2.0Max:7.0 year(s)
Information Technology/IT
IT Software - Network Administration / Security
Information Technology
MSc
Electrical, Electrical Engineering, Engineering
Proficient
1
Porto, Portugal