Senior ASIC Design Engineer

at  NVIDIA

We are now looking for a Senior ASIC Design Engineer!
NVIDIA is seeking outstanding Senior ASIC Designer to design and implement the power efficient and performance leading GPU’s. Push the state of the art in memory subsystem design. This position offers the opportunity to have a real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What You’ll Be Doing:

• In this role you will be responsible for the implementation of cache controllers and datapaths in the GPU memory subsystem.
• As a key member of the design team, you will collaborate closely with Architecture, Software, ASIC, Verification and VLSI teams to study, devise and implement efficient memory system designs for GPU
• Translate higher level feature requests into viable solutions for our GPU products.
• Define architectural and micro-architectural details for solutions delivering optimal Performance-per-Watt.
• Own RTL coding, synthesis, timing and power analysis of memory system functional blocks.
• Document, execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets

What we need to see:

• Bachelors or Masters Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
• At least 8 years of relevant work or research experience.
• Highly proficient in logic design, Verilog and/or System-Verilog, with a good understanding of Computer Architecture and Digital Systems design.
• A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis, floor-planning, System-On-Chip design/integration flow, and design automation.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Great communication and teamwork skills to interact within the team and across functional teams to build consensus.

Ways to stand out from the crowd:

• Specialization related to cache architectures, coherency, arbitration and SRAM layout.
• Familiarity with memory subsystem concepts such as memory management, cache consistency model, arbitration policies, high-speed IO protocols and/or on-chip interconnect.
• Good debugging and analytical skills.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.
The base salary range is 164,000 USD - 304,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
You will also be eligible for equity and
benefits
. NVIDIA accepts applications on an ongoing basis.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

• In this role you will be responsible for the implementation of cache controllers and datapaths in the GPU memory subsystem.
• As a key member of the design team, you will collaborate closely with Architecture, Software, ASIC, Verification and VLSI teams to study, devise and implement efficient memory system designs for GPU
• Translate higher level feature requests into viable solutions for our GPU products.
• Define architectural and micro-architectural details for solutions delivering optimal Performance-per-Watt.
• Own RTL coding, synthesis, timing and power analysis of memory system functional blocks.
• Document, execute and deliver fully verified, high performance, area and power efficient RTL to achieve design target