Senior/Principal Design Verification Engineer
at lowRISC CIC
Cambridge CB2 1GE, , United Kingdom -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 01 Jan, 2025 | GBP 96632 Annual | 03 Oct, 2024 | N/A | Gitlab,Engineers,C,Python,Security,Formal Verification,Gerrit,Git,Automation,Github,Code Review | No | No |
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Description:
CANDIDATE REQUIREMENTS
Essential:
- 5 years+ prior industry experience of design verification including significant SystemVerilog and UVM usage
- Experience across the full verification cycle from initial planning to final tape out
- Confident providing work estimates and coordinating work with a project manager
- Comfortable working with engineers across multiple organisations in multidisciplinary teams
- Undergraduate degree in a technical discipline or equivalent experience
Desirable:
- Broad experience range with background across multiple types of hardware blocks
- Understanding of security countermeasures against attacks such as fault injection or side-channel analysis
- Experience working with the RISC-V ISA or other instruction sets
- Familiarity with Git and code review using services such as GitHub, GitLab or Gerrit
- Programming using C and/or Python in tests and automation
- Formal verification with tools such as JasperGold
For the Principal role:
- Experience with leading a team or being a primary technical contributor in a major project
Responsibilities:
THE ROLE
In this role you will have the opportunity to apply industrial-strength design verification to high quality open source code bases. We are raising the bar for verification of open source projects to meet the highest commercial standards. Your focus will be on the verification of the range of open source designs we are producing for the future iterations of OpenTitan. This includes a RISC-V core (Ibex), a separate special purpose CPU for cryptographic operations, an AES accelerator and a variety of peripherals (such as USB, I2C and SPI).
You will:
- Design, implement and debug block-level and system-level tests and testbenches using SystemVerilog and UVM
- Stay up to date with the latest best practices and bring innovations to lowRISC
- Develop test and coverage plans for new or updated silicon designs
- Actively review contributions to our open source projects
- Triage and debug nightly regressions
- Contribute to the ongoing design and development of our test and continuous integration infrastructure
- Collaborate with partners to author papers for academic and industry conferences
For the Principal role:
- Experience with leading a team or being a primary technical contributor in a major projec
REQUIREMENT SUMMARY
Min:N/AMax:5.0 year(s)
Information Technology/IT
IT Software - Application Programming / Maintenance
Information Technology
Graduate
Proficient
1
Cambridge CB2 1GE, United Kingdom