Senior Verification Engineer

at  Envisics

Here at Envisics, we are an internationally based innovator in the automotive industry specialising in the development and supply of holographic technologies to Tier 1s and OEMs, with or our primary focus currently on augmented reality (“AR”) Head-up displays (“HUDs’).
Envisics’ holographic platform, which leverages a combination of complex materials science and proprietary algorithms, enables unparalleled performance as it relates to optimising both OEM manufacturing requirements and the end user experience.
We’ve already assembled some of the world’s top scientists & engineers from worldwide renowned companies and due to the success and growth of our product development activities, Envisics is now looking to invest in the talent of a Senior Validation and Verification Engineer to be part of the Core Engineering Team, developing and enhancing new and existing Hardware for our next generation Head-Up Displays.

As well as being part of a truly unique team at Envisics, your technical abilities will be put to the test as you will be a key part in development and setup of verification environments. You will be get involved with Regression Tests, Complex FPGA system simulations as well as taking part in and leading code reviews. Part of this role will also see you designing tests for functional correctness as well as implementing verification test cases for FPGAs and ASICs.

• Generate and maintain Vplan(s).
• Construct testbenches at different levels(unit, multi-unit and top-level) from scratch.
• Create test cases to verify block functionalities.
• Create and integrate reference models(e.g. SV model, Python model or Matlab model).
• Plan verification activities according to project timeline and deadlines.
• Run simulations and regressions and, track verification progress according to the Vplan.
• Construct coverage plans to reflect design requirements.
• Manage resources including tool chain maintenance, licence server handling and verification tasks definition.
• Participate in and lead code reviews.
• Participate in FPGA validation and post debug processes.
• Engage in process refinement and improvement of ways of working.
• Provide feedback and suggestions for improvement and simplification to design teams.
• Engage with FPGA/ASIC vendors, third-party IP vendors and tool vendors regarding simulation and verification activities.