Serdes Digital Design & Verification Engineering Masters Intern

at  Synopsys

Synopsys technology is at the heart of innovations that are changing the way we live and work. Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips (SoC). We design latest connectivity solutions such USB, Ethernet, PCIe which are then integrated in our customers’ SoC. These SoCs are used in computing devices including game consoles, graphics processors, smartphones, servers, 5G base stations and many more.

AS PART OF OUR TEAM, YOU WILL GET EXPERIENCE IN:

• RTL coding, modeling of analog blocks, and writing testbenches in SystemVerilog for next generation PAM4 Serdes spanning multiple protocols like PCIe, Ethernet, USB
• Defining Clock/Reset domain crossing design constraints and evaluating violations using latest CDC/RDC tools
• Debugging RTL and gate-level simulation failures as well as firmware issues
• Verifying functional behavior through simulation in Verilog behavioral models

SKILL REQUIREMENTS:

• Excellent knowledge of digital design theory, semiconductor lifecycle and related topics
• Proficient in language such as C and Verilog
• Scripting experience with Perl, Python, Bash, or Csh is an asset.

EDUCATION REQUIREMENTS:

• Enrolled in masters/PhD Computer Engineering, or Electrical Engineering with focus on digital design, semiconductor and related topics.
• Include your transcripts along with your resume.

Please refer the Job description for details