Silicon Design Engineer III

at  Ascendion

EXPERIENCE A COMMUNITY OF CHANGE MAKERS!

Join a culture of high-performing innovators with endless ideas and a passion for tech. Our culture is the fabric of our company, and it is what makes us unique and diverse. The way we share ideas, learning, experiences, successes, and joy allows everyone to be their best at Ascendion.

MINIMUM QUALIFICATIONS:

• BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
• 4+ years of experience as a Digital Design Engineer.
• Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC
• Experience having worked on a design from scratch – code from the ground up (outline / provide project work, if available)
• Experience in RTL coding and coding for low power in ASICs.
• Experience in digital design µArchitecture
• Familiarity with Verilog and SystemVerilog coding
• Perl, Tcl and Python (or similar) scripting experience

PREFERRED SKILLS:

• MSEE/CS or equivalent experience
• Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs – experience working on coding for these industries (typically aligns with what this team is doing)
• Recent track record of projects where individual coded from ground up that were successfully taped out.
  Location: Remote
  Salary Range: The salary for this position is between $104,400 – $187,200 annually. Factors which may affect pay within this range may include geography/market, skills, education, experience, and other qualifications of the successful candidate.
  Benefits: The Company offers the following benefits for this position, subject to applicable eligibility requirements: [medical insurance] [dental insurance] [vision insurance] [401(k) retirement plan] [long-term disability insurance] [short-term disability insurance] [5 personal days accrued each calendar year. The Paid time off benefits meet the paid sick and safe time laws that pertains to the City/ State] [10-15 days of paid vacation time] [6 paid holidays and 1 floating holiday per calendar year] [Ascendion Learning Management System]

WANT TO CHANGE THE WORLD? LET US KNOW.

Tell us about your experiences, education, and ambitions. Bring your knowledge, unique viewpoint, and creativity to the table. Let’s talk!

PREFERRED SKILLS:

• RTL coding
  Digital design µArchitecture
  Verilog

JOB REQUIREMENTS

Silicon Design Engineer III

ABOUT THE ROLE:

• The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on uarchitecture development and perform RTL coding on the next version of our client’s IP.
• This individual will have the opportunity to work on block design implementation for an IP that is going into our client’s future AR products.
  Job Title:Silicon Design Engineer III

KEY RESPONSIBILITIES:

• Own ASIC IP RTL implementation for IP blocks.
• Ensure RTL written meets quality checks like Lint/CDC/RDC.
• Collaborate closely with design team members, technical leads and the architecture team to ensure the block meets the power and performance requirements.
• Collaborate closely with the verification team to develop test plans and review test coverage.
• Perform IP integration
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis.