SOC ASIC DV & Testbench Architecture

at  Advanced Micro Devices Inc

PREFERRED EXPERIENCE:

• ASIC design verification or methodology experience
• Good at C/C++, Ruby, SQL, Linux OS
• Familiarity with SystemVerilog and modern verification libraries like UVM
• Experience/Background in GPU and APU design / verification
• Experience in design verification methodology is a benefit
• Experience is a benefit
• Proven experience of the latest design verification methodology such as assertion coverage based driven verification (code & functional coverage), constraint random test generation, and formal verification
• Strong problem solving skill, analytical skill and communication skill
• Good people and project management skills.
• Must be able to turn a problem into solution proposal and drive technical discussion.
• Ability to work well in a dynamic, fast-paced, pressure filled environment.
• Flexible in terms of responsibilities and hours. Enjoy superlarge project scope and complexity.

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to AI / ML market.

KEY RESPONSIBILITIES:

• A truly multi-disciplinary functions, working in close collaboration with architects, front-end designers, design verification engineers and methodology engineers to develop a testbench architecture and flows.
• Assist and organize IP integration scope, deliverables and deployment plans
• Define top level and interoperability testplans, chiplet and subsystem verification methodologies.
• Roll out necessary checks and signoff criteria
• Interact with third party IP and tool vendors as required.
• Develop testbench components in UVM and C++ to support various system level verification and coverage closure, including but not limited to system configuration, coherency, multi-engines.
• Build and improve current test libraries to enhance hierarchal integration flow and reusability from one SOC to another.
• Manage simulation performance
• Provide technical support to other teams on infrastructure backbone.
• Coach interns and junior members
• Assist project director and program manager on issues tracking across functional domain teams