SOC Logic Senior Staff Design Engineer

at  Intel

JOB DESCRIPTION

• DDG internal IP RTL design/development OR high performance/bandwidth IP integration into SOC.

• Define and implement new features, change requests/improvements on existing features for the IP.

• Drive and ensure IP-SOC handoff quality assurance and compliance.
• Perform logic/RTL integration into SOC, define power intent strategy, handling of signals crossing power planes and clock domains; along with other FE collateral for system/software integrations.
• Perform design exercise, collaborate with verification team for functional/feature/integration validation.
• Perform FE Quality checks in various logic design aspect ranging from RTL static checks to RTL synthesizability check, timing/power convergence, netlist quality check, Formal Equivalent Verification and many more.

QUALIFICATIONS

• Candidates should have a minimum of a Bachelor or Master Degree in Electrical & Electronic or Computer Science Engineering with at least 7 years working experiences in IP or SOC RTL/Logic Design.

• Knowledge in one or more of the following domains:

• IP/Subsystem/SOC architecture, I/O architecture, industry standard high speed bus protocols
• Industry exposure and knowledge of SoC/ASIC design methodology
• SOC system fabric and interconnect design
• Proficient in RTL design using Verilog/System Verilog
• Knowledge in industry FE/RTL tools and design methodologies
• System integration dealing with Si/Platform/FW/OS
• Experience with scripting/firmware/system-software development
• Experience with Post-Si lab debug/power on
• Should be willing to be a Mentor and Technical leader as part of your daily job, ability to work with different teams, good communication and problem solving skills
• Additional expectations are improving SOC design processes/methodology, creating a productive work environment, and being a catalyst for high quality output from the team

Please refer the Job description for details