SOC RTL Design and Integration, Senior Engineer
at Synopsys
Dublin, County Dublin, Ireland -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 18 Jan, 2025 | Not Specified | 20 Oct, 2024 | 3 year(s) or above | Semiconductors,Rtl Design,Integration | No | No |
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Description:
At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation and System-On-Chip (SoC) Design, we want to meet you.
The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification and physical implementation expertise to enable leading edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SOCs for high-performance computing, automotive, aerospace & defense, and more.
SOC RTL Design and Integration, Senior Engineer
JOB DESCRIPTION AND REQUIREMENTS
The role is for SoC RTL Design and Integration of IP/Subsystem/SoC Design in the System Solutions Group (SSG).
As part of this role, you can expect to develop and deliver your expertise in SoC Micro-Architecture, RTL Design, Subsystem or SoC Integration while working on RTL Signoff activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality. The role will expose you to various innovative technologies deployed for Semiconductors.
Responsibilities:
- Perform RTL Quality Signoff Checks such as LINT, CDC, RDC.
- Understand the design/architecture and develop timing constraints for synthesis and timing.
- Run preliminary synthesis to ensure that the design can be synthesized as intended.
- Run formality to ensure equivalence of RTL and gates.
- Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer.
REQUIREMENT SUMMARY
Min:3.0Max:8.0 year(s)
Information Technology/IT
Engineering Design / R&D
Information Technology
Graduate
Engineering
Proficient
1
Dublin, County Dublin, Ireland