SPE Systems Architecture
at Rambus
San Jose, CA 95134, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 02 Jan, 2025 | USD 303700 Annual | 07 Oct, 2024 | 12 year(s) or above | Smbus,Application Engineers,Engineers,I2C,System Architecture | No | No |
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Description:
Overview:
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior Principal Engineer to join our Memory Interface Chip team in San Jose. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
As a Senior Principal Engineer, the candidate will be reporting to VP of Engineering and is a Full Time position. The candidate will be part of an Architecture team for the new high performance Analog devices such as Register Clock Driver ((M)RCD), Data Buffer ((M)DB), Clock Driver (CKD) and DDR5 PMICs as well as other new memory technologies to help grow the business for the Memory Interface Chip Business Unit.
Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.
Responsibilities:
- Develop next generation of system/product architecture and definition
- Lead detail specification document with description, timing diagrams, flow diagrams, tables, illustrations, etc.
- Work with design, verification and test team for product development
- Interface with broad customer base and marketing team to develop the product definition
- Participate in industry standard organization to develop the standard
Qualifications:
- Master’s Degree or Ph.D. with 12+ years of professional experience
- Strong background in Server Memory Sub-system Architecture
- Familiarity with DDR5 DRAM, DDR5 (M)RCD, DDR5 (M)DB, DDR5 PMICs, DDR5 DIMM topologies and overall, DIMM operation
- Familiarity with High-Speed Analog Circuit Design Blocks, RTL design and Verification principles
- Familiarity with industry standard interface protocol such as I3C, I2C, SMBus
- Strong specification documentation skills
- Interface with design and verification engineers
- Interface with bench and ATE debug and test engineers
- Interface with application engineers
Responsibilities:
- Develop next generation of system/product architecture and definition
- Lead detail specification document with description, timing diagrams, flow diagrams, tables, illustrations, etc.
- Work with design, verification and test team for product development
- Interface with broad customer base and marketing team to develop the product definition
- Participate in industry standard organization to develop the standar
REQUIREMENT SUMMARY
Min:12.0Max:17.0 year(s)
Information Technology/IT
Engineering Design / R&D
Information Technology
Graduate
Proficient
1
San Jose, CA 95134, USA