Sr, Hardware Development Engineer

at  VIAVI Solutions

Summary:
VIAVI (NASDAQ: VIAV) is a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. VIAVI is also a leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications.
We are the people behind the products that help keep the world connected at home, school, work, at play, and everywhere in between. VIAVI employees are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.
Duties & Responsibilities:
As an FPGA Development Engineer, you will be responsible for developing new and maintaining existing FPGA designs and HDL components. Our designs contain numerous interfaces (memory, interconnect, IC control), signal processing functions and bit rate processing functions, primarily targeted at a 3GPP capable (4G/5G/future 6G) UE simulator.

Key Responsibilities

• Designing and documenting HDL components and interfaces
• Implementing HDL components using VHDL
• Testing HDL components in simulation
• Writing MATLAB code as a signal processing reference
• Building and timing closing FPGAs designs
• Debugging system issues seen on the target, determining FPGA based root causes and providing solutions
• Work with existing frameworks and systems
• Attending meetings and providing work breakdowns, estimates and progress updates
• Participate in cross team technical discussions on requirements and solutions

Pre-Requisites / Skills / Experience Requirements:

Your skills and qualifications will ideally include:

• Degree level qualification in relevant Engineering discipline
• Strong VHDL skills
• MATLAB programming skills
• Experience in component level test creation, execution and debug in a simulator
• Signal processing and channel coding implementation experience
• Experience building and timing closing large modern FPGAs designs
• Practical knowledge of high-speed interface protocols (e.g. Ethernet, PCIe, SRIO, other)
• Practical target debugging experience in a lab/customer environment
• Experience with 3GPP physical layer (4G/5G)
• High attention to detail
• Ability to solve various issues using a variety of methods and techniques
• Proven ability to work with very little input
• Proven analytical and problem-solving skills
• Proficient collaboration and team working skills, with the ability to develop and maintain strong productive relationships
• Proven communication skills, both verbal and written
• The ability to work within multiple projects simultaneously to meet deadlines, both independently and as part of a team

If you have what it takes to push boundaries and seize opportunities, apply to join our team today

• Designing and documenting HDL components and interfaces
• Implementing HDL components using VHDL
• Testing HDL components in simulation
• Writing MATLAB code as a signal processing reference
• Building and timing closing FPGAs designs
• Debugging system issues seen on the target, determining FPGA based root causes and providing solutions
• Work with existing frameworks and systems
• Attending meetings and providing work breakdowns, estimates and progress updates
• Participate in cross team technical discussions on requirements and solution