Sr. Memory Layout Engineer (6277)

at  TSMC

SKILLS

• Hands-on working knowledge of CAD tools; expert user of at least one large CAD custom layout tool flow
• Ability to deliver high quality layouts creatively and independently
• Demonstrated knowledge writing scripts and software macros to enhance productivity as required
• Significant experience with an APR (automated place and route) ASIC backend flow is advantageous
• Exceptional time management skills and work habits
• Proven ability to learn and adapt to new processes and design styles or constraints
• A team player with enhanced communication skills; excellent working knowledge of English (written and oral) is mandatory.
• Ability to work well with teams in diverse locations (e.g., USA, Taiwan)

KEY QUALIFICATIONS

• Undergrad/master’s degree in Computer Science, Computer Engineering, Physics, Mathematics, or a related discipline
• 6+ years of experience in A&MS Layout design
• Exceptional ability to analyze and problem-solve
• Well established listening, understanding, and responding skills, and ability to appreciate and interact with cross-functional teams
• Talent in layout design, verification, and documentation of complex analog and mixed signal circuits
• Highly developed attention to detail and multi-tasking skills

REQUIRED PRACTICAL EXPERIENCE ON

• Advanced FinFET nodes, TSMC 16 nanometer and below
• OTP or other types of memory layout design
• Layout techniques to meet ESD, latch up, antenna requirements
• Signal integrity issues in A&MS layout designs
• Verification tools: ICV, Calibre
• Design tool(s): Custom Compiler, Cadence Virtuoso or equivalent
• Scripting language: TCL, etc. (optional)

EDUCATION

• BSc EE or equivalent preferred
  Company Description
  TSMC Design Technology Canada (TDTC) is in the High-Tech area of Ottawa, Ontario. TDTC is focused on the research and design of deep sub-micron circuits to better serve and support the manufacturing needs of our foundry customers and 3rd party vendors.
  TSMC Design Technology Canada Inc, is a wholly owned subsidiary of TSMC in Taiwan.

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC North America obtaining any export license or other approval that may be required by the U.S. Government.

OVERVIEW OF ROLE

Do you want to work on leading edge future technologies, solving innovative next generation circuit problems, enabling many customer products into mass production?
This career opportunity is with TSMC Design Technology Canada Inc., located in Canada’s beautiful capital of Ottawa, Ontario. This unique opportunity is to join a high performing design team responsible for delivering the biggest and most complex TSMC compiler designs on the market.

RESPONSIBILITIES

In the role of Senior Memory Layout Engineer, you will primarily be responsible for challenging custom layout design and be involved in R&D projects implemented on the world’s most advanced CMOS/FinFET processes (5nm and below). This will involve detailed implementation of the high speed and high-density memory compilers and high-speed analog circuits. The successful candidate must demonstrate a high level of ability to estimate, plan and coordinate layout work.
You will perform custom layout implementing IC design in deep-submicron CMOS/FinFET. In addition, you will accomplish compact high performance memory layout: Memory Array, Periphery and Tiler Coding, etc. using industry standard custom CAD tools, layout, DRC, LVS, RC Extraction etc.