STA/Timing Engineer (Physical / Digital Design)

at  Kandou Bus

STA/Timing Engineer (Physical / Digital Design)
Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We’re an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a STA/Timing Engineer (Physical/Digital Design) based in either Dortmund-Germany, Lausanne-Switzerland, Northampton-UK or Copenhagen-Denmark.

The Role:

• As a STA/Timing Engineer, you will work closely with the Architecture and RTL team to ensure first-time-right high-volume silicon production
• Timing Constraints development, timing constraints validation, sign-off Static Timing Analysis and support for full chip & block-level timing closure will be the primary focus and responsibility
• Block and chip level STA with all aspects, reviewing and defining constraints with the design team, implementing SDC constraints to be used for block and chip (flat) STA, analyze violations and clean with help of frontend design and PD team
• Participate in developing improvements to scripts/methodologies/flows
• Interact closely with the design team to understand requirements and implement solutions for STA
• Support IP and chip level integration

‪The Person:

• Good knowledge of RTL to GDS implementation flow (synthesis, P&R, LEC, STA)
• Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
• Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)
• Experience in gathering and defining SDC constraints, specifically on top-level incl. DFT. Requires great team-work, tenacity, stamina and eye-for-detail. Also requires excellent communication and people skills to pull information from team members.
• Flow development with focus on cross project reusability

‪Preferred Experience:

• 10+ years’ experience in the semiconductor industry, with min. 5yrs in a technical Digital/Physical Design role.
• Experience on modern semiconductor process technologies such as, 28nm, 22nm, 16nm, 7nm, 3nm
• User of EDA tools for design and verification such as, Cadence Tempus, Quantus (QRC), Genus and LEC, etc
• Expertise in Timing/SDC constraints generation and management
• Experience in SDC verification tools – such as Fishtail
• Expertise in running hierarchical and flat static timing analysis incl. cross talk SI/glitch analysis

‪Academic Credentials:

• ‪ Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It

• As a STA/Timing Engineer, you will work closely with the Architecture and RTL team to ensure first-time-right high-volume silicon production
• Timing Constraints development, timing constraints validation, sign-off Static Timing Analysis and support for full chip & block-level timing closure will be the primary focus and responsibility
• Block and chip level STA with all aspects, reviewing and defining constraints with the design team, implementing SDC constraints to be used for block and chip (flat) STA, analyze violations and clean with help of frontend design and PD team
• Participate in developing improvements to scripts/methodologies/flows
• Interact closely with the design team to understand requirements and implement solutions for STA
• Support IP and chip level integratio