Staff CAD Engineer - Analog/RF Design Automation
at Silicon Labs Careers
Austin, Texas, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 23 Apr, 2025 | USD 252200 Annual | 23 Jan, 2025 | 8 year(s) or above | Symphony,Scripting Languages,Spectre,Perl,Pdk Development,Python | No | No |
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Description:
We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
Meet the Team
Be part of a highly skilled CAD Engineering team, critical to the success of Silicon Lab’s next generation of innovative product offerings!
Responsibilities
- Develop and maintain internal automation flows to enable and optimize product development cycle
- Support existing Analog/RF/AMS RF 3rd party simulation and verification tools and flows and be an interface between tool vendors and Silicon Labs
- Contribute to CAD publications and trainings to ensure that designers are updated on CAD-supported flows
- Troubleshoot and debug simulation problems and resolve them through detailed analysis
- Perform tool evaluations/benchmarks
Skills You Will Need
Minimum qualifications:
- M.S. or Ph.D. in Electrical Engineering with 8+ years of professional experience
- Strong CAD-flow automation experience using scripting languages such as Python, Perl, shell, SKILL, Ocean
- Strong familiarity with Analog/RF/AMS design and simulation tools and flows (e.g. Virtuoso, ADE Explorer/Assembler, Spectre, AFS, AMSD, Symphony)
The following qualifications will be considered a plus:
- Familiarity with using SPICE and Verilog-A models
- Familiarity with PDK development
- Familiarity with reliability analysis such as EMIR and aging
- Familiarity with AMS real number modeling
- Familiarity with IBIS modeling
- Familiarity with BSIM modeling based on Silicon data
Benefits & Perks
You can look forward to the following benefits:
- Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
- Highly competitive salary
- 401k plan with match and Roth plan option
- Equity rewards (RSUs)
- Employee Stock Purchase Plan (ESPP)
- Life/AD&D and disability coverage
- Flexible spending accounts
- Adoption assistance
- Back-Up childcare
- Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
- Flexible PTO schedule
- 3 paid volunteer days per year
- Charitable contribution match
- Tuition reimbursement
- Free downtown parking
- Onsite gym
- Monthly wellness offerings
- Free snacks
- Monthly company updates with our CEO
The annualized base pay range for this role is expected to be between $135,800 - $252,200 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status
Responsibilities:
- Develop and maintain internal automation flows to enable and optimize product development cycle
- Support existing Analog/RF/AMS RF 3rd party simulation and verification tools and flows and be an interface between tool vendors and Silicon Labs
- Contribute to CAD publications and trainings to ensure that designers are updated on CAD-supported flows
- Troubleshoot and debug simulation problems and resolve them through detailed analysis
- Perform tool evaluations/benchmark
REQUIREMENT SUMMARY
Min:8.0Max:13.0 year(s)
Information Technology/IT
Engineering Design / R&D
Information Technology
Graduate
Proficient
1
Austin, TX, USA