System Architecture Team, Sr. Staff Engineer

at  Synopsys

System Architecture Team, Sr. Staff Engineer
You will be part of an R&D team developing 32Gbps NRZ and 112Gbps PAM4 serial-link transceivers. Specifically, you will be responsible for modelling, design, analysis, and algorithms the transmitter and receiver mixed signal (analog and digital) front-end. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. You will work with a cross functional design team of analog and digital designers, and hardware engineers.

DUE TO THE CROSS DISCIPLINARY NATURE OF THIS POSITION, KEY QUALIFICATIONS INCLUDE ONE OR MORE OF THE FOLLOWING:

• Modelling - experience in Matlab/C/systemVerilog modeling of circuits and systems
• Analog – background in high-speed analog CMOS circuit design
• Digital – experience with DSP
• Hardware – awareness on per-protocol handing of RX and TX adaptation ; hands on experience in measurement of transceiver performance
• Communications theory – equalization, coding, noise/crosstalk filtering

BENEFICIAL EXPERIENCE:

• Experience in analyzing link budgets for either NRZ and PAM4 high-speed serial links
• Familiarity with modelling of SERDES transmitters and receivers in Matlab or similar tool
• Knowledge of circuit topologies in high-speed Rx/Tx SerDes PHY
• Understanding of Tx/Rx equalization techniques.
• Knowledge of CDR architectures and CDR loop dynamics
• Knowledge about common high-speed serial data protocols including PCIe, Ethernet, JESD, and CPRI
• Experience in lab testing of high-speed serial links

Please refer the Job description for details