Test & Validation Engineer, Senior - SerDes

at  Synopsys

Pavia, Lombardia, Italy -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate04 Dec, 2024Not Specified07 Sep, 2024N/AIp Solutions,MatlabNoNo
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Description:

JOB DESCRIPTION AND REQUIREMENTS

Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs.
As a SERDES Silicon Validation Engineer working in a lab environment, you will be responsible for product qualification and compliance to supported standards/specifications. You will be part of an R&D team developing high speed SerDes PHYs. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. Our R&D test lab contains high speed equipment such as: 112Gb/s capable BERTs, 70 GHz Oscilloscopes, and 85GHz Sampling Scopes

KEY REQUIREMENTS:

  • A BS degree in electrical or electronics engineering or in an appropriate related engineering discipline
  • Analog IC circuit basic understanding
  • Software programming experience
  • Knowledge and experience with Matlab
  • Debugging skills

Responsibilities:

  • Work with a cross functional design team of analog designers, systems designers, application engineers, and customers to resolve problems and demonstrate product performance.
  • Review and explain circuit behavior and circuit limitations in a testing and characterization environment.
  • Define test requirements and methodologies to validate silicon under test against target specifications.
  • Running characterization tests and creating test reports.
  • Debugging of electronic circuits; investigating product nonconformance.


REQUIREMENT SUMMARY

Min:N/AMax:5.0 year(s)

Electrical/Electronic Manufacturing

Engineering Design / R&D

Other

BSc

Electrical, Engineering

Proficient

1

Pavia, Lombardia, Italy