VHDL Developer

at  TXT esolutions SPA

Roma, Lazio, Italy -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate01 May, 2025Not Specified02 Feb, 20254 year(s) or aboveC++,Computer Engineering,MicroblazeNoNo
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Description:

TXT Group is an international, IT end-to-end provider of consultancy, software solutions and services, supporting the digital transformation of customers’ products and core processes. With a proprietary software portfolio and deep expertise in vertical domains, TXT Group operates across different markets, with a growing footprint in Aerospace, Aviation, Defense, Industrial, Government and Fintech. The holding company, TXT e-Solutions, has been listed on the Italian Stock Exchange - STAR segment (TXT.MI) - since July 2000. TXT Group headquartered in Milan and has subsidiaries in Italy, Germany, the United Kingdom, France, Switzerland and the United States of America.

VHDL DEVELOPER:

In this moment of strong expansion, TXT e-Tech, a company belonging to TXT Group, is looking for a VHDL Developer with at least four years of experience for an opportunity in the field of military radars.
All activities will take place in a context of international collaboration.

XILINX FPGA EXPERIENCE:

Familiarity with Artix-7, Kintex-7, Zynq and later FPGAs;
Experience with Xilinx IP Core and automatic generation tools (IP Integrator, Block Design).

OPTIONAL TECHNICAL SKILLS:

Experience with MicroBlaze or soft-core RISC-V on FPGAs
Knowledge of HLS (High-Level Synthesis) for FPGA design in C++;
Experience with tools for the analysis of the power and thermals of FPGA devices;
Knowledge of DO-254 for the certification of FPGA systems in the avionics/military field;
Experience with formal verification tools for FPGAs.
Required education: Bachelor’s or Master’s degree in computer engineering or similar.
The ideal candidate is a proactive person with strong skills in problem solving and team working.

Responsibilities:

VHDL FPGA design of Military Radars;
Creation of VHDL testbenches for functional verification;
Use of the Xilinx Vivado tool for synthesis, place & route, and bitstream generation;
Debugging and optimizing FPGA power and resource consumption;
Verification and Validation.


REQUIREMENT SUMMARY

Min:4.0Max:9.0 year(s)

Information Technology/IT

IT Software - Application Programming / Maintenance

Software Engineering

Graduate

Engineering

Proficient

1

Roma, Lazio, Italy