JOB DESCRIPTION

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the analog design of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Identifies, diagnoses, and improves the analog design flow, customizes efficient mixed signal design for different IPs, and develops automated flows for timing, power, and clock networks. Supports development of internal solutions to automate setup and execution of analog and mixed signal (AMS) simulations and resolves AMS simulation and modeling issues to continuously improve design execution. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing Analog Design related TFM. Works with custom level/transistor level analog, mixed signal, and RF designers to improve custom design methodology and ensure expected behavior of AMS/SoC block.

DesignEnablement

QUALIFICATIONS

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

The candidate’s responsibilities include (but are not limited to):

• Develop tools/flows to automate layout and/or schematic to generate testcases
• Develop testcases to validate design collaterals
• Collaborate with and provide layout feedback to designers and process engineers
• Troubleshoot and provide technical support to users as needed

Minimum Qualifications:

Candidate must possess a master’s with 3+ years of experience or Ph. D degree with 1+ years of experience in Electrical Engineering, Computer Engineering, or a related discipline.

• Experience in analog design using Virtuoso and Custom Compiler
• Experience in physical verification flows: LVS and DRC.

Preferred Qualifications:

• Hands-on foundry experience and expertise in developing and validating PDK collaterals
• Possess an understanding of technology design rules, circuit design knowledge and parser development
• Experience with CAD tools like Cadence Virtuoso/Synopsys Custom Designer, Cadence Spectre/Synopsys Hspice, Synopsys Star-RC and Synopsys IC Validator/Mentor Calibre.

• Develop tools/flows to automate layout and/or schematic to generate testcases
• Develop testcases to validate design collaterals
• Collaborate with and provide layout feedback to designers and process engineers
• Troubleshoot and provide technical support to users as neede