Applications Engineer (Custom Analog) - Design Enablement
at Intel
Santa Clara, California, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 22 Jul, 2024 | USD 159109 Annual | 29 Apr, 2024 | 1 year(s) or above | Computer Engineering,Perl,Addition,Python | No | No |
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Description:
JOB DESCRIPTION
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure design-kit leadership for customer enablement on cutting edge technologies, work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs. This support role will drive the solutions for analog layout using parameterized cells, analog collateral/tools/flows when customers use Intel PDK.
In this position you will also lead the collaboration and communication across TD/DE organizations to find the best path to resolve the issue, including owning/maintaining training documents, user guide, and customer ticket support. As a key member of the DEAS (Design Enablement Application and Support) team, you will leverage your communication skills to interact with customers directly, apply analytical problem-solving capability to identify the key requests, root-causing the issue, and do teamwork with DE stakeholders to support and enable customer success.
The position has the following focus areas:
- Custom layout/Custom flows domain to be able to understand and apply the technical concepts, systems, development methods, and drive solutions for the customer.
- Framing the project objectives, focuses, and navigates effort to solve problems, remove roadblocks, manages risks, schedules, drives recommendations to align senior management.
- Overseeing and identifying tasks, research, dependencies, and expectations to team members.
- Ensures that appropriate progress is in motion against schedule and takes remedial action as appropriate.
- Manages interdependencies and integration among multiple teams and stakeholders.
Design Enablement
QUALIFICATIONS
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or related STEAM field.
3+ years of experience in two or more of the following:
- Semiconductor device physics.
- Circuit simulation and custom analog flows and methodologies.
- Internal Intel or External Design Kit (PDK) Experience
- Custom analog tool suite usage such as Cadence ADE or similar tool suite.
- Basic scripting/automation experience.
Preferred Qualifications:
Developing parameterized cells and layout templates highly desired
1+ years of experience in two or more of the following:
- Analog layout
- Python or Perl for Automation Validation.
- Foundry experience.
- SKILL Language
- External EDA vendor interaction.
Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:1.0Max:3.0 year(s)
Information Technology/IT
IT Software - Other
Information Technology
BSc
Electrical, Electrical Engineering, Engineering
Proficient
1
Santa Clara, CA, USA